Memory devices include certain controls that affect the overall operation of the memory device. In particular, a memory device will generally include a Reset control to reset the memory device and a CKE (clock enable) control to disable and enable internal clock distribution of the memory device, and such controls will be engaged providing a signal to certain dedicated pins of the memory device. In a conventional memory device, when a certain signal is detected on the Reset pin, the memory device will perform a reset sequence. When a certain signal is detected on the CKE pin, the memory device turn off internal clock distribution, with the device ignoring clock operation.
However, as memory devices increase in complexity, the number of available pins for memory operations is reduced. In particular, a memory having multiple channels requires a large number of pins for operation, and the use of reset and CKE on dedicated pins is multiplied by the number of channels.
For example, a Wide IO DRAM (Dynamic Random Access Memory) device may be implemented with 16 independent channels. In such a device, the reset and CKE functions thus require 32 pins, which have a significant effect on the available pin count on such a device.